Integrated circuits use dielectric layers, which have typically been formed from silicon dioxide, SiO2, to insulate conductive lines on various layers of a semiconductor structure. As semiconductor circuits become faster and more compact, operating frequencies increase and the distances between the conductive lines within the semiconductor device decrease. This introduces an increased level of coupling capacitance to the circuit, which has the drawback of slowing the operation of the semiconductor device. Therefore, it has become important to use dielectric layers that are capable of effectively reducing the coupling capacitance levels in the circuit.
In general, the capacitance in an integrated circuit is directly proportional to the dielectric constant, k, of the material used to form the dielectric layers. As noted above, the dielectric layers in conventional integrated circuits have traditionally been formed of SiO2, which has a dielectric constant of about 4.0. Dielectric layers formed of SiO2 do not reduce the coupling capacitances sufficiently to levels required for increasing device densities and operating frequencies. In an effort to reduce the coupling capacitance levels in integrated circuits, the semiconductor industry has engaged in research to develop materials having a dielectric constant lower than that of SiO2, which materials are suitable for use in forming the dielectric layers in integrated circuits. To date, a number of promising materials, which are sometimes referred to as “low-k materials”, have been developed. Many of these new dielectrics are organic compounds. In the specification and claims, the definition of a low-k material, is a material with a dielectric constant less than 3.
Low-k materials include, but are specifically not limited to: benzocyclobutene or BCB; Flare™ manufactured by Allied Signal® of Morristown, N.J., a division of Honeywell, Inc., Minneapolis, Minn.; one or more of the Parylene dimers available from Union Carbides Corporation, Danbury Conn.; polytetrafluoroethylene or PTFE; and SiLK®. One PTFE suitable for IC dielectric application is SPEEDFILM™, available from W. L. Gore & Associates, Inc, Newark, Del. SiLK®, available from the Dow®Chemical Company, Midland, Mich., is a silicon-free BCB.
During semiconductor wafer processing, features of the semiconductor device are defined in the wafer using well known patterning and etching processes. In these processes a photoresist (PR) material is deposited on the wafer and then is exposed to light filtered by a reticle. The reticle is generally a glass plate that is patterned with exemplary feature geometries that blocked light from propagating through the reticle.
After passing through the reticle, the light contacts the surface of the photoresist material. The light changes the chemical composition of the photoresist material such that a developer can remove a portion of the photoresist material. In the case of positive photoresist materials the exposed regions are removed, and in the case of negative photoresist materials the unexposed regions are removed. Thereafter the wafer is etched to remove the underlying material from the areas that are no longer protected by the photoresist material and thereby define the desired features in the wafer. Low-k organic polymers in general can be etched by oxidation (e.g. oxygen-based) or reduction (e.g. hydrogen-based) chemical processes.
The etching of organic low-k dielectrics may be advantageously accomplished in a dual-frequency capacitively-coupled (DFC) dielectric etch system. One such is Lam® Research model 4520XLE™, available from Lam® Research Corporation, Fremont Calif. The 4520XLE™ system processes an extremely comprehensive dielectric etch portfolio in one system. Processes include contacts, vias, bilevel contacts, borderless contacts, nitride and oxide spacers, and passivation.
Advanced etch systems like the 4520XLE™ perform several processes in the same system. By performing many different semiconductor fabrication steps in a single system, wafer throughput can be increased. Even further advanced systems contemplate the performance of additional steps within the same equipment. Again by way of example, but not limitation, Lam® Research Corporation's Exelan™ and Exelan-HP™ systems are dry etch systems capable of performing many process steps in a single apparatus. Exelan™ enables hardmask open, inorganic and organic ARC etch, and photoresist strip to be performed in situ with a single chamber. This system's extensive process portfolio includes all dual damascene structures, contacts, vias, spacers, and passivation etch in doped and undoped oxides and low-k dielectrics required in the sub-0.18 micron environment. Of course, the principles enumerated herein may be implemented in wide variety of semiconductor fabrication systems, and these principles specifically contemplate all such alternatives.
As used herein, the term in situ refers to one or more processes performed on a given substrate, such as a silicon wafer, in the same piece of semiconductor fabrication equipment without removing the substrate from the equipment.
As discussed, the etching of organic low-k dielectrics may be accomplished using oxygen-based or hydrogen-based etching processes. Each of these is, however, less than ideal.
Hydrogen-based etching processes, e.g.: N2/H2 processes, are less than ideal for etching organic low-k dielectrics, particularly for etching the high-density features required in current sub-0.18 micron devices. This is true for a number of reasons. First, current N2/H2 processes offer generally slow etch rates and poor profile control of the etched features: bowing and re-entrant etch profiles are particular problems. Another problem relates to high aspect ratio features having differing sizes, which features are etched concurrently.
The etching of high aspect ratio trenches, sometimes referred to as HART, into low-k materials is becoming increasingly important for micro- and nano-engineering. One example is in the case of comb-driven structures, trench capacitors, and trench isolation for vertical transistors. The aspect ratio, AR, is defined as the depth of the trench divided by its width. Currently, one of the most commonly implemented techniques for etching HART's is dry reactive ion etching, or RIE.
When etching HART's with RIE it is observed that the etch rate is dependant on time and the mask opening. In general, smaller trench openings are etched more slowly than those that are wider. Accordingly, large features etch at a faster rate than small features. This effect is known as Aspect Ratio Dependent Etch (ARDE) or “RIE lag”. Known N2/H2 etch processes incur not only significant RIE lag, but more importantly, also exhibit etched profile angle dependence on feature size.
Another problem with known N2/H2 chemistries is that they have generally poor selectivity with respect to the oxides and nitrides commonly used as hard masks during etching. This means that the hard mask that should provide accurate feature definition is itself etched away fairly quickly during dielectric etch by the N2/H2 etch chemistry.
Another problem with N2/H2 plasmas is that in general they are stable only over fairly narrow ranges of pressure and power as a result of the high ionization potential of N2.
Finally, etching of organic low-k dielectrics with known N2/H2 processes is slow. This leads to reduced wafer throughput and increased cost of ownership of processing equipment for the integrated circuit manufacturer.
The slow etch rates obtainable by N2/H2 processes is often overcome using oxidative processes, most especially utilizing oxygen, O2 and a diluent such as nitrogen, N2. O2/N2 etch systems tend to possess much faster etch rates than N2/H2 systems, but are especially prone to bowing and can degrade the dielectric constant of the low-k dielectric. More troubling, they introduce a significant new problem, especially when utilized in conjunction with the manufacture of integrated circuit devices that incorporate copper.
Copper is currently being implemented as an interconnect material in favor of prior aluminum interconnect technologies. Copper offers several important advantages over aluminum. The higher conductivity of copper simplifies interconnect routing. This reduces the number of interconnect levels from 12 to 6, which removes upwards of 200 process steps and has a direct impact on device yield. Chips with copper interconnects operate with less power at a given frequency than chips with aluminum interconnects. Accordingly, copper interconnect technology enables devices with significantly higher performance for mobile applications. Finally, for very small features, the interconnect delay for copper and low-k materials is approximately one-half that of aluminum and SiO2. Copper interconnects are accordingly preferred for very small features because it provides speed enhancement with no sacrifice of device reliability.
Where copper in such devices is exposed to the etching environment, the use of an oxygen plasma often results in damage to the copper lines by generating copper-containing residue, which may deposit on the trench and via sidewalls causing copper contamination of the dielectric materials. Eventual migration of the copper to the transistor level of the device leads to failure of the device due to copper poisoning.
Many current integrated circuit fabrication technologies utilize a photoresist stripping step following one or more of the patterning steps used to form the features in the wafer. If a methodology could be found which not only completed a dielectric etch step, but simultaneously removed the photoresist from the surface of the wafer, a process step, that of the separate photoresist strip, could be eliminated. This of course would result in lower process times and higher throughput.
From the foregoing, a low-k etch process which implements higher etch rates than previous N2/H2 processes while avoiding the problems associated with prior N2/H2 processes would be very desirable.
It would also be very desirable to avoid the previously discussed problems with RIE lag, etch rate, and especially profile control.
It would moreover be very desirable to provide an etching process which exhibits a much higher degree of selectivity between the organic low-k dielectric and the hard mask required to form features through the dielectric. It would also be advantageous if the etch process could minimize the effect of “micro-masking” at the bottom of the etched feature. Micro-masking occurs when the etch process etches away a portion of the hard mask and subsequently re-deposits elements of the etched hard mask at the bottom of etched features.
It would be very advantageous if a dielectric etch process could be implemented which achieved the previous advantages while enabling a more stable etch plasma over a wider band of pressure and power operations than current N2/H2 processes.
In order to maintain a high wafer throughput, what is also desirable is that the methodology be capable of being performed in situ within the fabrication equipment utilized to form the wafer.
Finally, it would be very desirable if these advantages could be implemented using existing integrated circuit manufacturing equipment.
These and other features of the present invention will be described in more detail in the section entitled detailed description of the preferred embodiments and in conjunction with the following figures.